High speed decoder for flash memory

ABSTRACT

A word line driver for flash memories using NMOS circuitry to reduce parasitic capacitance loading on boost circuitry in low-voltage applications. A delay scheme which delays turn-on of the driver&#39;s source-drain circuit for a short time after the turn-on of the driver transistors&#39; gates allows the gate capacitance of the driver transistor to provide an extra boost.

FIELD OF THE INVENTION

[0001] This invention relates to decoders for flash memories, and moreparticularly to a fast xdecoder using NMOS driver circuitry incombination with a time delay scheme to insure efficient boostoperation.

BACKGROUND OF THE INVENTION

[0002] Flash memories conventionally consist of an array of floatinggate transistors or core cells that are arranged in blocks and areindividually addressable by energizing a specific word line and aspecific bit line of the array. A “0” on a core cell corresponds to ahigh turn-on threshold voltage on the order of 4V for the cell, while a“1” corresponds to a low turn-on threshold voltage on the order of 2V.The word line for each cell is connected to its transistor's controlgate, and the bit line for its address powers its source-drain circuit.A cell is read by driving its word line to a voltage between theabove-mentioned threshold voltages while its source-drain circuit isenergized. If current flows, the cell contains a “1”; if not, itcontains a “0.”

[0003] Traditionally, word line driver circuits for flash memories havebeen executed in CMOS topologies. These topologies have worked well withconventional robust V_(CC) sources of 5V or more, where parasitic cellcapacitances were not a significant consideration. In recent times,however, increasing miniaturization of electronics in general, and flashmemories in particular, have led to smaller V_(CC) supplies, on theorder of 3V.

[0004] Because of this lower V_(CC), it is necessary to use a voltageboosting circuit to provide a boost voltage V_(BST) to the control gate.Such a circuit is quite sensitive to parasitic capacitance loading. Itis in the nature of a CMOS driver for an xdecoder that is global wordline must be low in order for the cell to be selected. Consequently, theword lines of all unselected cells must be high, a condition which loadsthe boost circuit and slows it down. Thus, for fast operation, it isdesirable to provide a way of increasing boosting without loading theboost circuit.

SUMMARY OF THE INVENTION

[0005] The present invention solves the above-described problems byproviding word line drivers using NMOS transistors, in combination witha time-delay addressing scheme that uses the driver transistors' gatecapacitance to provide an extra boost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a circuit diagram showing a section of a flash memoryusing the invention;

[0007]FIG. 2 is a circuit diagram showing the word line driver of thisinvention;

[0008]FIG. 3 is a circuit diagram of a boost circuit useful in theinvention;

[0009]FIG. 4 is a circuit diagram of a global xdecoder in the invention;

[0010]FIG. 5 is a circuit diagram of the word line gate driver;

[0011]FIG. 6a and 6 b are circuit diagrams of a Vxdecoder used in theinvention; and

[0012]FIG. 7 is a set of time-amplitude diagrams illustrating thewaveforms encountered in the operation of the invention.

[0013]FIG. 1 illustrates a typical flash memory 10. The memory 10 isconventionally arranged in blocks 12 containing, for example, an arrayof 8×8 core cells or floating gate transistors 14. Each block 12includes a local xdecoder 16 whose inputs are a positive global wordline PGW, a negative global word line NGW, and (in FIG. 1) eightvertical word lines AVW₀ through AVW₇. The outputs of the local xdecoder16 are the word lines WL₀ through WL₇, each of which serves as the wordline for one horizontal row of core cells 14 in the block 12. Individualcore cells 14 of a given horizontal row are addressed by turning on aselected one of bit line transistors Y₀ through Y₇.

[0014]FIG. 2 shows the details of the local xdecoder 16 according to theinvention. For the 8×8 block of FIG. 1, there are eight drivers 20 ₀through 20 ₇ that produce the word line signals WL₀ through WL₇. Each ofthe drivers consists of a series-connected pair of n-transistors 22, 24and a word line gate n-transistor 26. The control gate of transistor 26is connected to a word line gate signal WLG whose generation isdescribed below in connection with FIG. 5.

[0015] If one local word line such as WL₀ is to be selected, PGW and WLGwill be high, and NGW will be low. If AVWL₀ goes from low to high underthose conditions, WL₀ will go up to AVWL₀ level. AVWL₀, WLG and PGW arebest supplied from a boost voltage source V_(BST) such as thatillustrated in FIG. 3. The boost voltage generator 30 may consist of aninverter 32 in series at node 38 with a boost capacitor 34 and inparallel with the gate-source circuit of an n-channel transistor 36.

[0016] A normally high kickback voltage V_(K) is applied to the input ofinverter 32 so that the V_(BST) output of capacitor 34 is connected toV_(CC) through transistor 36. When a cell is to be read, V_(K) goes low,node 38 goes high to V_(CC), and with transistor 36 now cut off, V_(BST)goes to V_(CC) plus the voltage stored on capacitor 34. After a readoperation, V_(K) returns to high and readies the circuit for the nextread operation.

[0017] In the inventive driver circuit, as pointed out above, only oneblock's PGW will be high to select a local word line such as WL₀.Inasmuch as PGW, WLG and AVWL are all supplied from V_(BST), the loadingcapacitance of the V_(BST) generator of FIG. 3 is minimized so as toallow high-speed word line driving.

[0018] Although the above-described circuit solves the V_(BST) loadingproblem, a special timing scheme is needed for optimum operation of theinventive circuit. Because pull-up transistors 22 and 24 are n-channeltransistors, the nodes 28 which are the gates of transistors 22 must bekept high enough to turn them on. In accordance with the invention, aself-boosting scheme is used. For this purpose, AVWL and WL are kept lowuntil the node 28 reaches a high enough voltage during the rise of PGWand WLG to the level of V_(BST). Then, when AVWL is allowed to rise toV_(BST), the voltage at node 28 is automatically boosted above V_(BST)due to the action of the channel capacitance of transistor 22.

[0019] Conventionally, a read operation is performed by an internal ATD(address transition detection) pulse generated whenever there is achange in the external address input. Thus, the kickback signal V_(K)discussed in connection with FIG. 3 above can advantageously be replacedby the ATD pulse, with V_(BST)=V_(CC) while ATD is high immediatelyafter the address change, and V_(BST) being boosted when ATD goes backto low after a short interval.

[0020] The ATD pulse is useful for a number of functions in theinventive circuit. FIG. 4 shows a global xdecoder 40 in accordance withthe invention. The external address is decoded by a NAND decode gate 42and is fed to the PGW generator consisting of transistors 44 a and 44 b.The output of NAND gate 42 also constitutes an input to NOR gate 46,whose other input is the ATD pulse. The output of NOR gate 46 isinverted in inverter 48 to form the NGW signal.

[0021] Thus, during the ATD pulse, NGW will be forced high while PGW isselected. During this time, the local word lines WL are forced low bytransistor 24 in FIG. 2. At the end of the ATD pulse, one of the NGWlines will be selected and go low, and the V_(BST) generator of FIG. 3will put out the boosted V_(BST) voltage. This makes the local decoderof FIG. 2 ready to drive the local word line WL.

[0022]FIG. 5 illustrates a preferred embodiment of the WLG driver. TheWLG signal is common in a vertical block. If that vertical block isselected, the WLG signal should be V_(BST), otherwise it should beV_(CC). This is accomplished as shown in FIG. 5. When the vertical blockof FIG. 5 is selected, the NAND gate 50 turns on n-channel transistor 51and forces the node 52 low. This turns on transistor 54 to pass V_(BST)to WLG while transistor 56 is off. If the block of FIG. 5 is notselected, node 52 is forced high, transistor 54 turns off, transistor 56turns on, and V_(CC) is applied to WLG. At the same time, transistor 58a turns off, 58 b turns on, and 58 c turns on, to boost node 52 forimproved operation of transistor 56.

[0023] Mention has been made above of the need to delay activation ofthe AVWL signal until the node 28 in FIG. 2 has had time to charge up toV_(BST), so that the channel capacitance of transistor 22 can charge upfor an extra boost. FIG. 6a shows a delay circuit 59 for carrying outthat task. In that figure, the selector NAND gate 60 has an additionalinput Nd, which is the ATD pulse stretched out by inverters 62 a, 62 b,capacitor 64, and NOR gate 66. An alternative version of the delaycircuit 59 is shown in FIG. 6b, in which Nd is simply the invertedsignal of node 38 in FIG. 3.

[0024] Nd goes low when ATD or 38 goes high, and returns to high with adelay time after the end of the ATD pulse. Thus, even though aparticular AVWL has been selected, it will stay low (68 a on, 68 b off,68 c off) until Nd goes high again (68 a off, 68 b on, 68 c on). Thisallows time for the gate capacitance of transistor 22 to charge up andcouple up its gate voltage when AVWL changes from low (0V) to high(V_(BST) ).

[0025]FIG. 7 shows the time relationships, in the operation of theinventive circuit, of the various signals described herein.

What is claimed is:
 1. Addressing circuitry for flash memories,comprising: a) a V_(cc) power supply; b) a boost circuit arranged toperiodically generate from said power supply a boost voltage greaterthan V_(cc); c) xdecoder circuitry driven by said boost voltage toaddress selected word lines of said memory, said xdecoder circuitrybeing so arranged that only one word line is high for any given addressso as to minimize the parasitic capacitance load on said boost circuit.2. The addressing circuitry of claim 1, in which said xdecoder comprisesNMOS circuitry.
 3. The addressing circuitry of claim 1, furthercomprising vertical xdecoder circuitry also driven by said boostvoltage, said vertical xdecoder also being so arranged that only onevertical word line is high for any given address.
 4. Addressingcircuitry for block-type flash memories, comprising: a) a global wordline associated with each row of blocks; and b) a local word lineassociated with each row of memory cells within a block; c) said localword line being powered by a vertical word line driver including a pairof series-connected transistors whose control gates are controlled by aglobal word line driver; d) the timing of said drivers being so arrangedthat said control gates are actuated on a predetermined time before thesource-drain circuit of said transistors is powered, whereby the voltagebuilt up in the transistors' channel capacitance by actuation of saidcontrol gates provides a turn-on boost for said transistors when theirsource-drain circuit becomes powered.
 5. In a flash memory laid out inan array of blocks each containing an array of core cells, each row ofblocks being associated with a separate global word line with positiveand negative rails, each row of cells within a block having a local wordline, and each row of cells within a block being associated with aseparate vertical word line, a local xdecoder comprising: a) first andsecond n-transistors connected in series between one of said verticalword lines and ground, said local word line being connected between saidfirst and second transistors; b) the gate of said first transistor beingconnected to the positive rail of said global word line through a wordline gate transistor; and c) the gate of said second transistor beingconnected to the negative rail of said global word line.
 6. The xdecoderof claim 5, in which said global word line, said word line gate, andsaid vertical word line are supplied by a boost voltage source.
 7. Aglobal xdecoder for outputting a positive rail and a negative rail of aglobal word line, comprising: a) a decode gate whose output is high whenselected; b) a source of address transition detection signals whichpulses high following selection of an address; c) a source of boostvoltage, said source being at V_(cc) supply voltage during the addresstransition detection pulse but rising to a boost voltage following theaddress transition detection pulse; d) a p-channel transistor and ann-channel transistor connected in series from said boost voltage sourceto ground, the gates of said transistors being connected together andbeing operatively connected to the output of said decode gate; e) saidpositive rail of said global word line being connected to theinterconnection of the source-drain circuits of said transistors; f) ap-channel boosting transistor connected between said boost voltagesource and said connected gates of said first-named transistors, thegate of said boosting transistor being connected to said positive rail;g) a NOR gate whose inputs are the output of said decode gate and saidaddress transition detection pulse, and h) an inverter connected toinvert the output of said NOR gate to form said negative rail of saidglobal word line.
 8. A word line gate driver for flash memories,comprising: a) a word line gate signal output; b) a vertical blockselect decode gate, the output of said gate being high when the verticalblock corresponding to said word line gate is selected; c) a source ofboost voltage, said source being at V_(cc) supply voltage during theaddress transition detection pulse but rising to a boost voltagefollowing the address transition detection pulse; d) a p-channeltransistor and an n-channel transistor connected in series from saidboost voltage source to ground, the gates of said transistors beingconnected together and being operatively connected to the output of saiddecode gate; e) a p-channel boosting transistor connected between saidboost voltage source and said connected gates of said first-namedtransistors, the gate of said boosting transistor being connected to theinterconnection of the source-drain circuits of said first-namedtransistors; f) p-channel and n-channel switching transistors havingtheir gates connected to said interconnection of the source-draincircuits of said first-named transistors; g) the source-drain circuit ofsaid p-channel switching transistor being connected between said boostvoltage source and said word line gate signal output; and h) thesource-drain circuit of said n-channel switching transistor beingconnected between said V_(cc) supply voltage and said word line gatesignal output.
 9. A vertical xdecoder for flash memories, comprising: a)a vertical word line signal output; b) a vertical word line selectdecode gate, said gate being a NAND gate with selection line inputs andan additional input; c) said additional input being connected to adetection pulse so delayed that said additional input goes low at theleading edge of said pulse but goes high a predetermined length of timeafter the trailing edge of said pulse: d) a source of boost voltage,said source being at V_(cc) supply voltage during the address transitiondetection pulse but rising to a boost voltage following the addresstransition detection pulse; e) a p-channel transistor and an n-channeltransistor connected in series from said boost voltage source to ground,the gates of said transistors being connected together and beingoperatively connected to the output of said decode gate; f) a p-channelboosting transistor connected between said boost voltage source and saidconnected gates of said first-named transistors, the gate of saidboosting transistor being connected to said vertical word line signaloutput; and g) said vertical word line signal output being connected tothe interconnection between said first-named transistors in theirsource-drain circuit.